👍
dmgCm3_bgp_change_sprites.gb
👍
dmgCm3_lcdc_bg_en_change.gb
👍
dmgCm3_lcdc_bg_map_change.gb
👍
dmgCm3_lcdc_obj_en_change.gb
👍
dmgCm3_lcdc_obj_en_change_variant.gb
👍
dmgCm3_lcdc_obj_size_change.gb
👍
dmgCm3_lcdc_obj_size_change_scx.gb
👍
dmgCm3_lcdc_tile_sel_change.gb
👍
dmgCm3_lcdc_tile_sel_win_change.gb
👍
dmgCm3_lcdc_win_en_change_multiple.gb
👍
dmgCm3_lcdc_win_en_change_multiple_wx.gb
👍
dmgCm3_lcdc_win_map_change.gb
👍
dmgCm3_scx_high_5_bits.gb
👍
dmgCm3_scx_low_3_bits.gb
👍
dmgCm3_window_timing_wx_0.gb
👍
dmgCm3_wx_4_change_sprites.gb
👍
dmgCly-GScgb0ABC.gb
![Passed](img/dmgC_ly-GScgb0ABC.png)
👍
dmgCmbc3_rtc_prelim.gb
![mbc3_rtc_prelim
$01 $00 $01 $00
$00 $3B $40 $00
$00 $00 $3B $00
$00 $00 $01 $00
$00 $00 $01 $00
$00 $00 $01 $00
$00 $00 $01 $00
$00 $00 $00 $80
$00 $00 $00 $00
$01 $00 $00 $3B
$01 $00 $01 $00
$10 $20 $00 $00
$C1 $1F $3F $3F
Passed](img/dmgC_mbc3_rtc_prelim.png)
👍
dmgCoam_dma_bus_conflicts-GS.gb
![Passed](img/dmgC_oam_dma_bus_conflicts-GS.png)
👍
dmgCstat-GScgb0ABC.gb
![Passed](img/dmgC_stat-GScgb0ABC.png)
👍
dmgCvblank_int_timing-GS.gb
![vblank_int_timing-GS
$01 $00 $01 $00
$01 $00 $01 $00
$01 $00 $01 $00
Passed](img/dmgC_vblank_int_timing-GS.png)
👍
cgbChdma_during_halt.gb
![hdma_during_halt
$03 $04 $05 $06
$C6 $C2 $C2 $C2
$01 $00 $FF $FF
$11 $BE $BE $BE
$22 $22 $EF $EF
$03 $04 $05 $06
$C6 $C2 $C2 $C2
$01 $00 $FF $FF
$11 $BE $BE $BE
$22 $22 $EF $EF
Passed](img/cgbC_hdma_during_halt.png)
👍
cgbChdma_timing.gb
![hdma_timing
$83 $80 $80 $82
$00 $FF $FF $FF
$83 $80 $80 $82
$00 $00 $FF $FF
$01 $02 $01 $02
$03 $04 $03 $04
$83 $80 $80 $82
$00 $FF $FF $FF
$83 $80 $80 $82
$00 $00 $FF $FF
$03 $04 $03 $04
$07 $08 $07 $08
Passed](img/cgbC_hdma_timing.png)
👍
cgbCly-GScgb0ABC.gb
![Passed](img/cgbC_ly-GScgb0ABC.png)
👍
cgbCstat-GScgb0ABC.gb
![Passed](img/cgbC_stat-GScgb0ABC.png)
👍
cgbCstat_2x-C.gb
![Passed](img/cgbC_stat_2x-C.png)
👍
cgbCstat_2x_scx1-C.gb
![Passed](img/cgbC_stat_2x_scx1-C.png)
👍
cgbCstat_2x_scx2-C.gb
![Passed](img/cgbC_stat_2x_scx2-C.png)
👍
cgbCstat_2x_scx3-C.gb
![Passed](img/cgbC_stat_2x_scx3-C.png)
👍
cgbCvblank_int_timing-C.gb
![vblank_int_timing-C
$01 $00 $01 $00
$01 $00 $01 $00
$01 $00 $01 $00
Passed](img/cgbC_vblank_int_timing-C.png)
👍
cgbCbg_color_palette.gbc
![Passed](img/cgbC_bg_color_palette.png)
👍
cgbCdouble_speed.gbc
![Passed](img/cgbC_double_speed.png)
👍
cgbCgdma.gbc
![Passed](img/cgbC_gdma.png)
👍
cgbCoam_dma_bus_conflicts-C.gbc
![Passed](img/cgbC_oam_dma_bus_conflicts-C.png)
👍
cgbCobj_color_palette.gbc
![Passed](img/cgbC_obj_color_palette.png)
👍
cgbCvram_bank.gbc
![Passed](img/cgbC_vram_bank.png)
👍
cgbCwram_bank-cgbBCDEagb0.gbc
![Passed](img/cgbC_wram_bank-cgbBCDEagb0.png)
👍
cgbEhdma_during_halt.gb
![hdma_during_halt
$03 $04 $05 $06
$C6 $C2 $C2 $C2
$01 $00 $FF $FF
$11 $BE $BE $BE
$22 $22 $EF $EF
$03 $04 $05 $06
$C6 $C2 $C2 $C2
$01 $00 $FF $FF
$11 $BE $BE $BE
$22 $22 $EF $EF
Passed](img/cgbE_hdma_during_halt.png)
👍
cgbEhdma_timing.gb
![hdma_timing
$83 $80 $80 $82
$00 $FF $FF $FF
$83 $80 $80 $82
$00 $00 $FF $FF
$01 $02 $01 $02
$03 $04 $03 $04
$83 $80 $80 $82
$00 $FF $FF $FF
$83 $80 $80 $82
$00 $00 $FF $FF
$03 $04 $03 $04
$07 $08 $07 $08
Passed](img/cgbE_hdma_timing.png)
👍
cgbEly-cgbDEagbags.gb
![Passed](img/cgbE_ly-cgbDEagbags.png)
👍
cgbEstat-cgbDEagbags.gb
![Passed](img/cgbE_stat-cgbDEagbags.png)
👍
cgbEstat_2x-C.gb
![Passed](img/cgbE_stat_2x-C.png)
👍
cgbEstat_2x_scx1-C.gb
![Passed](img/cgbE_stat_2x_scx1-C.png)
👍
cgbEstat_2x_scx2-C.gb
![Passed](img/cgbE_stat_2x_scx2-C.png)
👍
cgbEstat_2x_scx3-C.gb
![Passed](img/cgbE_stat_2x_scx3-C.png)
👍
cgbEvblank_int_timing-C.gb
![vblank_int_timing-C
$01 $00 $01 $00
$01 $00 $01 $00
$01 $00 $01 $00
Passed](img/cgbE_vblank_int_timing-C.png)
👍
cgbEbg_color_palette.gbc
![Passed](img/cgbE_bg_color_palette.png)
👍
cgbEdouble_speed.gbc
![Passed](img/cgbE_double_speed.png)
👍
cgbEgdma.gbc
![Passed](img/cgbE_gdma.png)
👍
cgbEoam_dma_bus_conflicts-C.gbc
![Passed](img/cgbE_oam_dma_bus_conflicts-C.png)
👍
cgbEobj_color_palette.gbc
![Passed](img/cgbE_obj_color_palette.png)
👍
cgbEvram_bank.gbc
![Passed](img/cgbE_vram_bank.png)
👍
cgbEwram_bank-cgbBCDEagb0.gbc
![Passed](img/cgbE_wram_bank-cgbBCDEagb0.png)
👍
cgbEsprite_selection_and_draw_priority.gbc
👍
cgbCm3_bgp_change_sprites.gb
👍
cgbCm3_lcdc_bg_en_change.gb
👍
cgbCm3_lcdc_bg_en_change2.gb
👍
cgbCm3_lcdc_bg_map_change.gb
👍
cgbCm3_lcdc_bg_map_change2.gb
👍
cgbCm3_lcdc_obj_en_change.gb
👍
cgbCm3_lcdc_obj_en_change_variant.gb
👍
cgbCm3_lcdc_obj_size_change.gb
👍
cgbCm3_lcdc_obj_size_change_scx.gb
👍
cgbCm3_lcdc_tile_sel_change.gb
👍
cgbCm3_lcdc_tile_sel_change2.gb
❌
cgbCm3_lcdc_tile_sel_win_change.gb - 328 pixels differ
Expected:
![](img/expected_cgbC_m3_lcdc_tile_sel_win_change.png)
Result:
![](img/cgbC_m3_lcdc_tile_sel_win_change.png)
Difference:
![](img/difference_cgbC_m3_lcdc_tile_sel_win_change.png)
👍
cgbCm3_lcdc_tile_sel_win_change2.gb
👍
cgbCm3_lcdc_win_en_change_multiple.gb
❌
cgbCm3_lcdc_win_en_change_multiple_wx.gb - 23040 pixels differ
Expected:
![](img/expected_cgbC_m3_lcdc_win_en_change_multiple_wx.png)
Result:
![](img/cgbC_m3_lcdc_win_en_change_multiple_wx.png)
Difference:
![](img/difference_cgbC_m3_lcdc_win_en_change_multiple_wx.png)
👍
cgbCm3_lcdc_win_map_change.gb
👍
cgbCm3_lcdc_win_map_change2.gb
👍
cgbCm3_scx_high_5_bits.gb
👍
cgbCm3_scx_high_5_bits_change2.gb
👍
cgbCm3_scx_low_3_bits.gb
❌
cgbCm3_window_timing.gb - 6 pixels differ
Expected:
![](img/expected_cgbC_m3_window_timing.png)
Result:
![](img/cgbC_m3_window_timing.png)
Difference:
![](img/difference_cgbC_m3_window_timing.png)
👍
cgbCm3_window_timing_wx_0.gb
❌
cgbCm3_wx_4_change.gb - 18648 pixels differ
Expected:
![](img/expected_cgbC_m3_wx_4_change.png)
Result:
![](img/cgbC_m3_wx_4_change.png)
Difference:
![](img/difference_cgbC_m3_wx_4_change.png)
👍
cgbCm3_wx_4_change_sprites.gb
❌
cgbCm3_wx_5_change.gb - 19811 pixels differ
Expected:
![](img/expected_cgbC_m3_wx_5_change.png)
Result:
![](img/cgbC_m3_wx_5_change.png)
Difference:
![](img/difference_cgbC_m3_wx_5_change.png)
❌
cgbCm3_wx_6_change.gb - 19809 pixels differ
Expected:
![](img/expected_cgbC_m3_wx_6_change.png)
Result:
![](img/cgbC_m3_wx_6_change.png)
Difference:
![](img/difference_cgbC_m3_wx_6_change.png)
👍
cgbDm3_bgp_change_sprites.gb
👍
cgbDm3_lcdc_bg_en_change.gb
👍
cgbDm3_lcdc_bg_map_change.gb
👍
cgbDm3_lcdc_obj_en_change.gb
👍
cgbDm3_lcdc_obj_en_change_variant.gb
👍
cgbDm3_lcdc_obj_size_change.gb
👍
cgbDm3_lcdc_obj_size_change_scx.gb
👍
cgbDm3_lcdc_tile_sel_change.gb
❌
cgbDm3_lcdc_tile_sel_win_change.gb - 328 pixels differ
Expected:
![](img/expected_cgbD_m3_lcdc_tile_sel_win_change.png)
Result:
![](img/cgbD_m3_lcdc_tile_sel_win_change.png)
Difference:
![](img/difference_cgbD_m3_lcdc_tile_sel_win_change.png)
👍
cgbDm3_lcdc_win_en_change_multiple.gb
❌
cgbDm3_lcdc_win_en_change_multiple_wx.gb - 23040 pixels differ
Expected:
![](img/expected_cgbD_m3_lcdc_win_en_change_multiple_wx.png)
Result:
![](img/cgbD_m3_lcdc_win_en_change_multiple_wx.png)
Difference:
![](img/difference_cgbD_m3_lcdc_win_en_change_multiple_wx.png)
👍
cgbDm3_lcdc_win_map_change.gb
👍
cgbDm3_scx_high_5_bits.gb
👍
cgbDm3_scx_low_3_bits.gb
❌
cgbDm3_window_timing.gb - 6 pixels differ
Expected:
![](img/expected_cgbD_m3_window_timing.png)
Result:
![](img/cgbD_m3_window_timing.png)
Difference:
![](img/difference_cgbD_m3_window_timing.png)
👍
cgbDm3_window_timing_wx_0.gb
❌
cgbDm3_wx_4_change.gb - 18648 pixels differ
Expected:
![](img/expected_cgbD_m3_wx_4_change.png)
Result:
![](img/cgbD_m3_wx_4_change.png)
Difference:
![](img/difference_cgbD_m3_wx_4_change.png)
👍
cgbDm3_wx_4_change_sprites.gb
❌
cgbDm3_wx_5_change.gb - 19811 pixels differ
Expected:
![](img/expected_cgbD_m3_wx_5_change.png)
Result:
![](img/cgbD_m3_wx_5_change.png)
Difference:
![](img/difference_cgbD_m3_wx_5_change.png)
❌
cgbDm3_wx_6_change.gb - 19809 pixels differ
Expected:
![](img/expected_cgbD_m3_wx_6_change.png)
Result:
![](img/cgbD_m3_wx_6_change.png)
Difference:
![](img/difference_cgbD_m3_wx_6_change.png)
👍
cgbEm3_bgp_change_sprites.gb
👍
cgbEm3_lcdc_bg_en_change.gb
👍
cgbEm3_lcdc_bg_map_change.gb
👍
cgbEm3_lcdc_obj_en_change.gb
👍
cgbEm3_lcdc_obj_en_change_variant.gb
👍
cgbEm3_lcdc_obj_size_change.gb
👍
cgbEm3_lcdc_obj_size_change_scx.gb
👍
cgbEm3_lcdc_tile_sel_change.gb
❌
cgbEm3_lcdc_tile_sel_win_change.gb - 328 pixels differ
Expected:
![](img/expected_cgbE_m3_lcdc_tile_sel_win_change.png)
Result:
![](img/cgbE_m3_lcdc_tile_sel_win_change.png)
Difference:
![](img/difference_cgbE_m3_lcdc_tile_sel_win_change.png)
👍
cgbEm3_lcdc_win_en_change_multiple.gb
❌
cgbEm3_lcdc_win_en_change_multiple_wx.gb - 23040 pixels differ
Expected:
![](img/expected_cgbE_m3_lcdc_win_en_change_multiple_wx.png)
Result:
![](img/cgbE_m3_lcdc_win_en_change_multiple_wx.png)
Difference:
![](img/difference_cgbE_m3_lcdc_win_en_change_multiple_wx.png)
👍
cgbEm3_lcdc_win_map_change.gb
👍
cgbEm3_scx_high_5_bits.gb
👍
cgbEm3_scx_low_3_bits.gb
❌
cgbEm3_window_timing.gb - 6 pixels differ
Expected:
![](img/expected_cgbE_m3_window_timing.png)
Result:
![](img/cgbE_m3_window_timing.png)
Difference:
![](img/difference_cgbE_m3_window_timing.png)
👍
cgbEm3_window_timing_wx_0.gb
❌
cgbEm3_wx_4_change.gb - 18648 pixels differ
Expected:
![](img/expected_cgbE_m3_wx_4_change.png)
Result:
![](img/cgbE_m3_wx_4_change.png)
Difference:
![](img/difference_cgbE_m3_wx_4_change.png)
👍
cgbEm3_wx_4_change_sprites.gb
❌
cgbEm3_wx_5_change.gb - 19811 pixels differ
Expected:
![](img/expected_cgbE_m3_wx_5_change.png)
Result:
![](img/cgbE_m3_wx_5_change.png)
Difference:
![](img/difference_cgbE_m3_wx_5_change.png)
❌
cgbEm3_wx_6_change.gb - 19809 pixels differ
Expected:
![](img/expected_cgbE_m3_wx_6_change.png)
Result:
![](img/cgbE_m3_wx_6_change.png)
Difference:
![](img/difference_cgbE_m3_wx_6_change.png)
Blargg's Tests
👍
cgbEcgb_sound.gb
![cgb_sound
01:ok 02:ok 03:ok
04:ok 05:ok 06:ok
07:ok 08:ok 09:ok
10:ok 11:ok 12:ok
Passed](img/cgbE_cgb_sound.png)
👍
cgbEinterrupt_time.gb
![interrupt time
00 00 00
00 08 0D
01 00 00
01 08 0D
Passed](img/cgbE_interrupt_time.png)
👍
dmgCcpu_instrs.gb
![cpu_instrs
01:ok 02:ok 03:ok
04:ok 05:ok 06:ok
07:ok 08:ok 09:ok
10:ok 11:ok
Passed all tests](img/dmgC_cpu_instrs.png)
👍
dmgCdmg_sound-2.gb
![dmg_sound
01:ok 02:ok 03:ok
04:ok 05:ok 06:ok
07:ok 08:ok 09:ok
10:ok 11:ok 12:ok
Passed](img/dmgC_dmg_sound-2.png)
👍
dmgChalt_bug.gb
![halt bug
IE IF IF DE
01 10 F1 0C04
01 00 E1 0C04
01 01 E1 0411
11 00 E1 0C04
11 10 F1 0411
11 11 F1 0411
E1 00 E1 0C04
E1 E0 E1 0C04
E1 E1 E1 0411
Passed](img/dmgC_halt_bug.png)
👍
dmgCinstr_timing.gb
![instr_timing
Passed](img/dmgC_instr_timing.png)
👍
dmgCmem_timing-2.gb
![mem_timing
01:ok 02:ok 03:ok
Passed](img/dmgC_mem_timing-2.png)
👍
dmgCoam_bug-2.gb
![oam_bug
01:ok 02:ok 03:ok
04:ok 05:ok 06:ok
07:ok 08:ok
Passed](img/dmgC_oam_bug-2.png)
👍
dmg0acceptance/boot_div-dmg0.gb
![Registers
A: 19 F: 00
B: 19 C: 1A
D: 1A E: 1B
H: 1C L: 1E
Assertions
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmg0_boot_div-dmg0.png)
👍
dmg0acceptance/boot_hwio-dmg0.gb
![Test OK](img/dmg0_boot_hwio-dmg0.png)
👍
dmgCacceptance/add_sp_e_timing.gb
![Registers
A: 40 F: 00
B: FF C: FD
D: 00 E: 40
H: FF L: CA
Assertions
B: OK C: OK
D: OK E: OK](img/dmgC_add_sp_e_timing.png)
👍
dmgCacceptance/bits/mem_oam.gb
![Test OK](img/dmgC_mem_oam.png)
👍
dmgCacceptance/bits/reg_f.gb
![Registers
A: 00 F: 00
B: 00 C: F0
D: 00 E: 00
H: 01 L: 4D
Assertions
C: OK
E: OK](img/dmgC_reg_f.png)
👍
dmgCacceptance/bits/unused_hwio-GS.gb
![Test OK](img/dmgC_unused_hwio-GS.png)
👍
dmgCacceptance/boot_div-dmgABCmgb.gb
![Registers
A: AC F: B0
B: AC C: AD
D: AD E: AE
H: AF L: B1
Assertions
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_boot_div-dmgABCmgb.png)
👍
dmgCacceptance/boot_hwio-dmgABCmgb.gb
![Test OK](img/dmgC_boot_hwio-dmgABCmgb.png)
👍
dmgCacceptance/boot_regs-dmgABC.gb
![Registers
A: 01 F: B0
B: 00 C: 13
D: 00 E: D8
H: 01 L: 4D
Assertions
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_boot_regs-dmgABC.png)
👍
dmgCacceptance/call_cc_timing.gb
![Test OK](img/dmgC_call_cc_timing.png)
👍
dmgCacceptance/call_cc_timing2.gb
![Registers
A: 00 F: 90
B: 81 C: 81
D: 81 E: B9
H: FF L: D6
Assertions
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_call_cc_timing2.png)
👍
dmgCacceptance/call_timing.gb
![Test OK](img/dmgC_call_timing.png)
👍
dmgCacceptance/call_timing2.gb
![Registers
A: 00 F: C0
B: 81 C: 81
D: 81 E: B9
H: FF L: D6
Assertions
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_call_timing2.png)
👍
dmgCacceptance/di_timing-GS.gb
![Test OK](img/dmgC_di_timing-GS.png)
👍
dmgCacceptance/div_timing.gb
![Registers
A: 01 F: 80
B: 00 C: 00
D: 01 E: D8
H: FF L: 04
Assertions
B: OK C: OK
D: OK](img/dmgC_div_timing.png)
👍
dmgCacceptance/ei_sequence.gb
![Registers
A: 00 F: 80
B: 01 C: A2
D: 00 E: D8
H: 01 L: 4D
Assertions
B: OK C: OK](img/dmgC_ei_sequence.png)
👍
dmgCacceptance/ei_timing.gb
![Registers
A: 00 F: 00
B: 01 C: 13
D: 00 E: 01
H: 01 L: 4D
Assertions
B: OK
E: OK](img/dmgC_ei_timing.png)
👍
dmgCacceptance/halt_ime0_ei.gb
![Test OK](img/dmgC_halt_ime0_ei.png)
👍
dmgCacceptance/halt_ime0_nointr_timing.gb
![Registers
A: 12 F: 80
B: 00 C: 13
D: 11 E: 12
H: 02 L: 04
Assertions
D: OK E: OK](img/dmgC_halt_ime0_nointr_timing.png)
👍
dmgCacceptance/halt_ime1_timing.gb
![Registers
A: 05 F: 80
B: 00 C: 13
D: 00 E: D8
H: 01 L: 4D
Assertions
B: OK](img/dmgC_halt_ime1_timing.png)
👍
dmgCacceptance/halt_ime1_timing2-GS.gb
![Registers
A: 12 F: 80
B: 11 C: 12
D: 11 E: 12
H: 02 L: 21
Assertions
B: OK C: OK
D: OK E: OK](img/dmgC_halt_ime1_timing2-GS.png)
👍
dmgCacceptance/if_ie_registers.gb
![Registers
A: E0 F: 00
B: 00 C: E8
D: 01 E: E0
H: FF L: 0F
Assertions
B: OK C: OK
D: OK E: OK](img/dmgC_if_ie_registers.png)
👍
dmgCacceptance/instr/daa.gb
![Test OK](img/dmgC_daa.png)
👍
dmgCacceptance/interrupts/ie_push.gb
![Test OK](img/dmgC_ie_push.png)
👍
dmgCacceptance/intr_timing.gb
![Registers
A: 01 F: 80
B: FF C: 04
D: 00 E: 01
H: 02 L: 0E
Assertions
D: OK E: OK](img/dmgC_intr_timing.png)
👍
dmgCacceptance/jp_cc_timing.gb
![Test OK](img/dmgC_jp_cc_timing.png)
👍
dmgCacceptance/jp_timing.gb
![Test OK](img/dmgC_jp_timing.png)
👍
dmgCacceptance/ld_hl_sp_e_timing.gb
![Registers
A: 80 F: 10
B: CF C: FE
D: D0 E: 3F
H: FF L: BB
Assertions
B: OK C: OK
D: OK E: OK](img/dmgC_ld_hl_sp_e_timing.png)
👍
dmgCacceptance/oam_dma/basic.gb
![Test OK](img/dmgC_basic.png)
👍
dmgCacceptance/oam_dma/reg_read.gb
![Test OK](img/dmgC_reg_read.png)
👍
dmgCacceptance/oam_dma/sources-dmgABCmgbS.gb
![Test OK](img/dmgC_sources-dmgABCmgbS.png)
👍
dmgCacceptance/oam_dma_restart.gb
![Registers
A: 01 F: C0
B: 00 C: FF
D: 01 E: 08
H: FE L: 00
Assertions
C: OK
D: OK](img/dmgC_oam_dma_restart.png)
👍
dmgCacceptance/oam_dma_start.gb
![Registers
A: 01 F: C0
B: D7 C: 01
D: D7 E: 00
H: 02 L: 38
Assertions
B: OK C: OK
D: OK E: OK](img/dmgC_oam_dma_start.png)
👍
dmgCacceptance/oam_dma_timing.gb
![Registers
A: 01 F: C0
B: 00 C: FF
D: 01 E: 08
H: FE L: 00
Assertions
C: OK
D: OK](img/dmgC_oam_dma_timing.png)
👍
dmgCacceptance/pop_timing.gb
![Registers
A: 01 F: F0
B: 00 C: 01
D: 00 E: 01
H: FF L: 04
Assertions
A: OK
B: OK C: OK
D: OK E: OK](img/dmgC_pop_timing.png)
👍
dmgCacceptance/ppu/hblank_ly_scx_timing-GS.gb
![Test OK](img/dmgC_hblank_ly_scx_timing-GS.png)
👍
dmgCacceptance/ppu/intr_1_2_timing-GS.gb
![Registers
A: 00 F: 00
B: 15 C: 13
D: 14 E: 15
H: FF L: 41
Assertions
D: OK E: OK](img/dmgC_intr_1_2_timing-GS.png)
👍
dmgCacceptance/ppu/intr_2_0_timing.gb
![Registers
A: 00 F: 00
B: 08 C: 13
D: 07 E: 08
H: FF L: 41
Assertions
D: OK E: OK](img/dmgC_intr_2_0_timing.png)
👍
dmgCacceptance/ppu/intr_2_mode0_timing.gb
![Registers
A: 00 F: A0
B: 02 C: 13
D: 01 E: 02
H: FF L: 41
Assertions
D: OK E: OK](img/dmgC_intr_2_mode0_timing.png)
👍
dmgCacceptance/ppu/intr_2_mode0_timing_sprites.gb
![Test OK](img/dmgC_intr_2_mode0_timing_sprites.png)
👍
dmgCacceptance/ppu/intr_2_mode3_timing.gb
![Registers
A: 03 F: C0
B: 02 C: 13
D: 01 E: 02
H: FF L: 41
Assertions
D: OK E: OK](img/dmgC_intr_2_mode3_timing.png)
👍
dmgCacceptance/ppu/intr_2_oam_ok_timing.gb
![Registers
A: 00 F: A0
B: 02 C: 00
D: 01 E: 02
H: FE L: 00
Assertions
D: OK E: OK](img/dmgC_intr_2_oam_ok_timing.png)
👍
dmgCacceptance/ppu/lcdon_timing-dmgABCmgbS.gb
![Test OK](img/dmgC_lcdon_timing-dmgABCmgbS.png)
👍
dmgCacceptance/ppu/lcdon_write_timing-GS.gb
![Test OK](img/dmgC_lcdon_write_timing-GS.png)
👍
dmgCacceptance/ppu/stat_irq_blocking.gb
![Test OK](img/dmgC_stat_irq_blocking.png)
👍
dmgCacceptance/ppu/stat_lyc_onoff.gb
![Test OK](img/dmgC_stat_lyc_onoff.png)
👍
dmgCacceptance/ppu/vblank_stat_intr-GS.gb
![Registers
A: 01 F: 80
B: 01 C: 00
D: 01 E: 00
H: FF L: 96
Assertions
B: OK C: OK
D: OK E: OK](img/dmgC_vblank_stat_intr-GS.png)
👍
dmgCacceptance/push_timing.gb
![Registers
A: 00 F: C0
B: 00 C: 00
D: 81 E: 24
H: 42 L: 24
Assertions
D: OK E: OK
H: OK L: OK](img/dmgC_push_timing.png)
👍
dmgCacceptance/rapid_di_ei.gb
![Registers
A: 00 F: 00
B: 00 C: 00
D: 01 E: 01
H: 01 L: 4D
Assertions
B: OK C: OK
D: OK E: OK](img/dmgC_rapid_di_ei.png)
👍
dmgCacceptance/ret_cc_timing.gb
![Test OK](img/dmgC_ret_cc_timing.png)
👍
dmgCacceptance/ret_timing.gb
![Test OK](img/dmgC_ret_timing.png)
👍
dmgCacceptance/reti_intr_timing.gb
![Registers
A: 00 F: 00
B: 01 C: 13
D: 01 E: 01
H: 01 L: 4D
Assertions
B: OK
D: OK E: OK](img/dmgC_reti_intr_timing.png)
👍
dmgCacceptance/reti_timing.gb
![Test OK](img/dmgC_reti_timing.png)
👍
dmgCacceptance/rst_timing.gb
![Registers
A: 00 F: C0
B: 81 C: 9E
D: FF E: BD
H: FF L: BD
Assertions
B: OK C: OK
D: OK E: OK](img/dmgC_rst_timing.png)
👍
dmgCacceptance/serial/boot_sclk_align-dmgABCmgb.gb
![Registers
A: 12 F: 00
B: 91 C: 90
D: 90 E: 90
H: 90 L: 90
Assertions
A: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_boot_sclk_align-dmgABCmgb.png)
👍
dmgCacceptance/timer/div_write.gb
![Test OK](img/dmgC_div_write.png)
👍
dmgCacceptance/timer/interrupts.gb
![Test OK](img/dmgC_interrupts.png)
👍
dmgCacceptance/timer/rapid_toggle.gb
![Registers
A: 00 F: 00
B: FF C: D9
D: 00 E: D8
H: 01 L: 4D
Assertions
B: OK C: OK](img/dmgC_rapid_toggle.png)
👍
dmgCacceptance/timer/tim00.gb
![Registers
A: 05 F: 80
B: 04 C: 13
D: 04 E: 05
H: 01 L: 4D
Assertions
D: OK E: OK](img/dmgC_tim00.png)
👍
dmgCacceptance/timer/tim00_div_trigger.gb
![Registers
A: 05 F: 80
B: 04 C: 13
D: 04 E: 05
H: 01 L: 4D
Assertions
D: OK E: OK](img/dmgC_tim00_div_trigger.png)
👍
dmgCacceptance/timer/tim01.gb
![Registers
A: 09 F: 80
B: 04 C: 13
D: 08 E: 09
H: 01 L: 4D
Assertions
D: OK E: OK](img/dmgC_tim01.png)
👍
dmgCacceptance/timer/tim01_div_trigger.gb
![Registers
A: 0B F: 80
B: 04 C: 13
D: 0A E: 0B
H: 01 L: 4D
Assertions
D: OK E: OK](img/dmgC_tim01_div_trigger.png)
👍
dmgCacceptance/timer/tim10.gb
![Registers
A: 05 F: 80
B: 04 C: 13
D: 04 E: 05
H: 01 L: 4D
Assertions
D: OK E: OK](img/dmgC_tim10.png)
👍
dmgCacceptance/timer/tim10_div_trigger.gb
![Registers
A: 06 F: 80
B: 04 C: 13
D: 05 E: 06
H: 01 L: 4D
Assertions
D: OK E: OK](img/dmgC_tim10_div_trigger.png)
👍
dmgCacceptance/timer/tim11.gb
![Registers
A: 05 F: 80
B: 04 C: 13
D: 04 E: 05
H: 01 L: 4D
Assertions
D: OK E: OK](img/dmgC_tim11.png)
👍
dmgCacceptance/timer/tim11_div_trigger.gb
![Registers
A: 05 F: 80
B: 04 C: 13
D: 04 E: 05
H: 01 L: 4D
Assertions
D: OK E: OK](img/dmgC_tim11_div_trigger.png)
👍
dmgCacceptance/timer/tima_reload.gb
![Registers
A: FE F: 80
B: FE C: FE
D: FF E: 00
H: FF L: 00
Assertions
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_tima_reload.png)
👍
dmgCacceptance/timer/tima_write_reloading.gb
![Registers
A: 7F F: 80
B: FE C: FE
D: 80 E: 7F
H: 7F L: 7F
Assertions
C: OK
D: OK E: OK
L: OK](img/dmgC_tima_write_reloading.png)
👍
dmgCacceptance/timer/tma_write_reloading.gb
![Registers
A: FE F: 80
B: FE C: FE
D: 7F E: 7F
H: 7F L: FE
Assertions
C: OK
D: OK E: OK
L: OK](img/dmgC_tma_write_reloading.png)
👍
dmgCemulator-only/mbc1/bits_bank1.gb
![Test OK](img/dmgC_bits_bank1.png)
👍
dmgCemulator-only/mbc1/bits_bank2.gb
![Test OK](img/dmgC_bits_bank2.png)
👍
dmgCemulator-only/mbc1/bits_mode.gb
![Test OK](img/dmgC_bits_mode.png)
👍
dmgCemulator-only/mbc1/bits_ramg.gb
![Test OK](img/dmgC_bits_ramg.png)
👍
dmgCemulator-only/mbc1/multicart_rom_8Mb.gb
![Test OK](img/dmgC_multicart_rom_8Mb.png)
👍
dmgCemulator-only/mbc1/ram_256kb.gb
![Test OK](img/dmgC_ram_256kb.png)
👍
dmgCemulator-only/mbc1/ram_64kb.gb
![Test OK](img/dmgC_ram_64kb.png)
👍
dmgCemulator-only/mbc1/rom_16Mb.gb
![Test OK](img/dmgC_rom_16Mb.png)
👍
dmgCemulator-only/mbc1/rom_1Mb.gb
![Test OK](img/dmgC_rom_1Mb.png)
👍
dmgCemulator-only/mbc1/rom_2Mb.gb
![Test OK](img/dmgC_rom_2Mb.png)
👍
dmgCemulator-only/mbc1/rom_4Mb.gb
![Test OK](img/dmgC_rom_4Mb.png)
👍
dmgCemulator-only/mbc1/rom_512kb.gb
![Test OK](img/dmgC_rom_512kb.png)
👍
dmgCemulator-only/mbc1/rom_8Mb.gb
![Test OK](img/dmgC_rom_8Mb.png)
👍
dmgCemulator-only/mbc2/bits_ramg.gb
![Test OK](img/dmgC_bits_ramg.png)
👍
dmgCemulator-only/mbc2/bits_romb.gb
![Test OK](img/dmgC_bits_romb.png)
👍
dmgCemulator-only/mbc2/bits_unused.gb
![Test OK](img/dmgC_bits_unused.png)
👍
dmgCemulator-only/mbc2/ram.gb
![Test OK](img/dmgC_ram.png)
👍
dmgCemulator-only/mbc2/rom_1Mb.gb
![Test OK](img/dmgC_rom_1Mb.png)
👍
dmgCemulator-only/mbc2/rom_2Mb.gb
![Test OK](img/dmgC_rom_2Mb.png)
👍
dmgCemulator-only/mbc2/rom_512kb.gb
![Test OK](img/dmgC_rom_512kb.png)
👍
dmgCemulator-only/mbc5/rom_16Mb.gb
![Test OK](img/dmgC_rom_16Mb.png)
👍
dmgCemulator-only/mbc5/rom_1Mb.gb
![Test OK](img/dmgC_rom_1Mb.png)
👍
dmgCemulator-only/mbc5/rom_2Mb.gb
![Test OK](img/dmgC_rom_2Mb.png)
👍
dmgCemulator-only/mbc5/rom_32Mb.gb
![Test OK](img/dmgC_rom_32Mb.png)
👍
dmgCemulator-only/mbc5/rom_4Mb.gb
![Test OK](img/dmgC_rom_4Mb.png)
👍
dmgCemulator-only/mbc5/rom_512kb.gb
![Test OK](img/dmgC_rom_512kb.png)
👍
dmgCemulator-only/mbc5/rom_64Mb.gb
![Test OK](img/dmgC_rom_64Mb.png)
👍
dmgCemulator-only/mbc5/rom_8Mb.gb
![Test OK](img/dmgC_rom_8Mb.png)
👍
cgb0misc/boot_div-cgb0.gb
![Registers
A: 29 F: 80
B: 29 C: 2A
D: 2A E: 2B
H: 2C L: 2E
Assertions
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgb0_boot_div-cgb0.png)
👍
cgbEmisc/bits/unused_hwio-C.gb
![Test OK](img/cgbE_unused_hwio-C.png)
👍
cgbEmisc/boot_div-cgbABCDE.gb
![Registers
A: 27 F: 80
B: 27 C: 28
D: 28 E: 29
H: 2A L: 2C
Assertions
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_boot_div-cgbABCDE.png)
👍
cgbEmisc/boot_hwio-C.gb
![Test OK](img/cgbE_boot_hwio-C.png)
👍
cgbEmisc/boot_regs-cgb.gb
![Registers
A: 11 F: 80
B: 00 C: 00
D: 00 E: 08
H: 00 L: 7C
Assertions
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_boot_regs-cgb.png)
👍
cgbEmisc/ppu/vblank_stat_intr-C.gb
![Registers
A: 01 F: 80
B: 01 C: 00
D: 01 E: 00
H: FF L: 96
Assertions
B: OK C: OK
D: OK E: OK](img/cgbE_vblank_stat_intr-C.png)
👍
cgbCacceptance/gpu/hblank_ly_scx_timing-C.gb
![TEST OK](img/cgbC_hblank_ly_scx_timing-C.png)
👍
cgbCacceptance/gpu/ly_lyc_0_write-C.gb
![REGISTERS
A: C2 F: C0
B: 00 C: 01
D: 01 E: 00
H: C2 L: C2
ASSERTIONS
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbC_ly_lyc_0_write-C.png)
👍
cgbCacceptance/gpu/ly_lyc_153_write-C.gb
![REGISTERS
A: C1 F: C0
B: 00 C: 01
D: 01 E: 00
H: C1 L: C1
ASSERTIONS
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbC_ly_lyc_153_write-C.png)
👍
cgbCacceptance/gpu/ly_lyc_write-C.gb
![REGISTERS
A: 07 F: 00
B: 00 C: 01
D: 01 E: 00
H: C2 L: C2
ASSERTIONS
A: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbC_ly_lyc_write-C.png)
👍
cgbCacceptance/gpu/stat_write_if-C.gb
![TEST OK](img/cgbC_stat_write_if-C.png)
👍
cgbEacceptance/gpu/hblank_ly_scx_timing-C.gb
![TEST OK](img/cgbE_hblank_ly_scx_timing-C.png)
👍
cgbEacceptance/gpu/ly00_mode1_2-cgbDE.gb
![REGISTERS
A: 98 F: 10
B: 99 C: 81
D: 00 E: 81
H: 00 L: 82
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_ly00_mode1_2-cgbDE.png)
👍
cgbEacceptance/gpu/ly_lyc-cgbDE.gb
![REGISTERS
A: 01 F: 20
B: C0 C: C6
D: E0 E: E2
H: C4 L: C2
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_ly_lyc-cgbDE.png)
👍
cgbEacceptance/gpu/ly_lyc_0-cgbDE.gb
![REGISTERS
A: 99 F: 00
B: 15 C: 13
D: 55 E: C6
H: 44 L: C2
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_ly_lyc_0-cgbDE.png)
👍
cgbEacceptance/gpu/ly_lyc_0_write-C.gb
![REGISTERS
A: C2 F: C0
B: 00 C: 01
D: 01 E: 00
H: C2 L: C2
ASSERTIONS
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_ly_lyc_0_write-C.png)
👍
cgbEacceptance/gpu/ly_lyc_144-cgbDE.gb
![REGISTERS
A: 8F F: 00
B: C0 C: C5
D: E0 E: E3
H: C5 L: C1
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_ly_lyc_144-cgbDE.png)
👍
cgbEacceptance/gpu/ly_lyc_153-cgbDE.gb
![REGISTERS
A: 98 F: 90
B: C1 C: C5
D: E1 E: E3
H: C5 L: C1
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_ly_lyc_153-cgbDE.png)
👍
cgbEacceptance/gpu/ly_lyc_153_write-C.gb
![REGISTERS
A: C1 F: C0
B: 00 C: 01
D: 01 E: 00
H: C1 L: C1
ASSERTIONS
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_ly_lyc_153_write-C.png)
👍
cgbEacceptance/gpu/ly_lyc_write-C.gb
![REGISTERS
A: 07 F: 00
B: 00 C: 01
D: 01 E: 00
H: C2 L: C2
ASSERTIONS
A: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_ly_lyc_write-C.png)
👍
cgbEacceptance/gpu/ly_new_frame-cgbDE.gb
![REGISTERS
A: 98 F: 10
B: 99 C: 81
D: 99 E: 81
H: 00 L: 81
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/cgbE_ly_new_frame-cgbDE.png)
👍
cgbEacceptance/gpu/stat_write_if-C.gb
![TEST OK](img/cgbE_stat_write_if-C.png)
👍
dmgCacceptance/boot_hwio-G.gb
![TEST OK](img/dmgC_boot_hwio-G.png)
👍
dmgCacceptance/gpu/hblank_ly_scx_timing_nops.gb
![TEST OK](img/dmgC_hblank_ly_scx_timing_nops.png)
👍
dmgCacceptance/gpu/hblank_ly_scx_timing_variant_nops.gb
![TEST OK](img/dmgC_hblank_ly_scx_timing_variant_nops.png)
👍
dmgCacceptance/gpu/intr_0_timing.gb
![REGISTERS
A: FF F: 80
B: E0 C: E0
D: E2 E: E2
H: FF L: FF
ASSERTIONS
B: OK C: OK
D: OK E: OK](img/dmgC_intr_0_timing.png)
👍
dmgCacceptance/gpu/intr_1_timing.gb
![REGISTERS
A: E3 F: 80
B: E0 C: FF
D: FF E: FF
H: E0 L: E0
ASSERTIONS
A: OK
B: OK
H: OK L: OK](img/dmgC_intr_1_timing.png)
👍
dmgCacceptance/gpu/intr_2_0_timing.gb
![REGISTERS
A: 00 F: 00
B: 08 C: 13
D: 07 E: 08
H: FF L: 41
ASSERTIONS
D: OK E: OK](img/dmgC_intr_2_0_timing.png)
👍
dmgCacceptance/gpu/intr_2_mode0_scx1_timing_nops.gb
![REGISTERS
A: 00 F: 00
B: 02 C: 01
D: 03 E: 00
H: FF L: 41
ASSERTIONS
B: OK C: OK
D: OK E: OK](img/dmgC_intr_2_mode0_scx1_timing_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_scx2_timing_nops.gb
![REGISTERS
A: 00 F: 00
B: 02 C: 01
D: 03 E: 00
H: FF L: 41
ASSERTIONS
B: OK C: OK
D: OK E: OK](img/dmgC_intr_2_mode0_scx2_timing_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_scx3_timing_nops.gb
![REGISTERS
A: 00 F: 00
B: 02 C: 01
D: 03 E: 00
H: FF L: 41
ASSERTIONS
B: OK C: OK
D: OK E: OK](img/dmgC_intr_2_mode0_scx3_timing_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_scx4_timing_nops.gb
![REGISTERS
A: 00 F: 00
B: 02 C: 01
D: 03 E: 00
H: FF L: 41
ASSERTIONS
B: OK C: OK
D: OK E: OK](img/dmgC_intr_2_mode0_scx4_timing_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_scx5_timing_nops.gb
![REGISTERS
A: 00 F: 00
B: 02 C: 01
D: 03 E: 00
H: FF L: 41
ASSERTIONS
B: OK C: OK
D: OK E: OK](img/dmgC_intr_2_mode0_scx5_timing_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_scx6_timing_nops.gb
![REGISTERS
A: 00 F: 00
B: 02 C: 01
D: 03 E: 00
H: FF L: 41
ASSERTIONS
B: OK C: OK
D: OK E: OK](img/dmgC_intr_2_mode0_scx6_timing_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_scx7_timing_nops.gb
![REGISTERS
A: 00 F: 00
B: 02 C: 01
D: 03 E: 00
H: FF L: 41
ASSERTIONS
B: OK C: OK
D: OK E: OK](img/dmgC_intr_2_mode0_scx7_timing_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_scx8_timing_nops.gb
![REGISTERS
A: 00 F: 00
B: 02 C: 01
D: 03 E: 00
H: FF L: 41
ASSERTIONS
B: OK C: OK
D: OK E: OK](img/dmgC_intr_2_mode0_scx8_timing_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_timing_sprites_nops.gb
![TEST OK](img/dmgC_intr_2_mode0_timing_sprites_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_timing_sprites_scx1_nops.gb
![TEST OK](img/dmgC_intr_2_mode0_timing_sprites_scx1_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_timing_sprites_scx2_nops.gb
![TEST OK](img/dmgC_intr_2_mode0_timing_sprites_scx2_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_timing_sprites_scx3_nops.gb
![TEST OK](img/dmgC_intr_2_mode0_timing_sprites_scx3_nops.png)
👍
dmgCacceptance/gpu/intr_2_mode0_timing_sprites_scx4_nops.gb
![TEST OK](img/dmgC_intr_2_mode0_timing_sprites_scx4_nops.png)
👍
dmgCacceptance/gpu/intr_2_timing.gb
![REGISTERS
A: E3 F: 80
B: E0 C: E0
D: E2 E: E2
H: E0 L: E2
ASSERTIONS
A: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_intr_2_timing.png)
👍
dmgCacceptance/gpu/lcdon_mode_timing.gb
![REGISTERS
A: 80 F: 30
B: 83 C: 80
D: 80 E: 82
H: 82 L: 83
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_lcdon_mode_timing.png)
👍
dmgCacceptance/gpu/ly00_01_mode0_2.gb
![REGISTERS
A: 82 F: C0
B: 00 C: 80
D: 01 E: 80
H: 01 L: 82
ASSERTIONS
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly00_01_mode0_2.png)
👍
dmgCacceptance/gpu/ly00_mode0_2-GS.gb
![REGISTERS
A: 98 F: 10
B: 99 C: 81
D: 00 E: 80
H: 00 L: 82
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly00_mode0_2-GS.png)
👍
dmgCacceptance/gpu/ly00_mode1_0-GS.gb
![REGISTERS
A: 98 F: 10
B: 99 C: 81
D: 00 E: 81
H: 00 L: 80
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly00_mode1_0-GS.png)
👍
dmgCacceptance/gpu/ly00_mode2_3.gb
![REGISTERS
A: 98 F: 10
B: 99 C: 81
D: 00 E: 82
H: 00 L: 83
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly00_mode2_3.png)
👍
dmgCacceptance/gpu/ly00_mode3_0.gb
![REGISTERS
A: 98 F: 10
B: 99 C: 81
D: 00 E: 83
H: 00 L: 80
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly00_mode3_0.png)
👍
dmgCacceptance/gpu/ly143_144_145.gb
![REGISTERS
A: 8F F: 30
B: 8F C: 80
D: 90 E: 81
H: 91 L: 81
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly143_144_145.png)
👍
dmgCacceptance/gpu/ly143_144_152_153.gb
![REGISTERS
A: 8F F: 30
B: 8F C: 80
D: 98 E: 81
H: 99 L: 81
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly143_144_152_153.png)
👍
dmgCacceptance/gpu/ly143_144_mode0_1.gb
![REGISTERS
A: 8F F: 30
B: 8F C: 80
D: 90 E: 80
H: 90 L: 81
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly143_144_mode0_1.png)
👍
dmgCacceptance/gpu/ly143_144_mode3_0.gb
![REGISTERS
A: 8F F: 30
B: 8F C: 80
D: 8F E: 80
H: 90 L: 80
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly143_144_mode3_0.png)
👍
dmgCacceptance/gpu/ly_lyc-GS.gb
![REGISTERS
A: 01 F: 20
B: C0 C: C6
D: E0 E: E2
H: C4 L: C0
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly_lyc-GS.png)
👍
dmgCacceptance/gpu/ly_lyc_0-GS.gb
![REGISTERS
A: 99 F: 00
B: 15 C: 13
D: 54 E: C6
H: 40 L: C2
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly_lyc_0-GS.png)
👍
dmgCacceptance/gpu/ly_lyc_0_write-GS.gb
![REGISTERS
A: C2 F: C0
B: 00 C: 01
D: 01 E: 00
H: C2 L: C2
ASSERTIONS
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly_lyc_0_write-GS.png)
👍
dmgCacceptance/gpu/ly_lyc_144-GS.gb
![REGISTERS
A: 8F F: 00
B: C0 C: C5
D: E0 E: E3
H: C5 L: C1
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly_lyc_144-GS.png)
👍
dmgCacceptance/gpu/ly_lyc_153-GS.gb
![REGISTERS
A: 98 F: 90
B: C1 C: C5
D: E1 E: E3
H: C5 L: C1
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly_lyc_153-GS.png)
👍
dmgCacceptance/gpu/ly_lyc_153_write-GS.gb
![REGISTERS
A: C1 F: C0
B: 00 C: 01
D: 01 E: 00
H: C1 L: C1
ASSERTIONS
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly_lyc_153_write-GS.png)
👍
dmgCacceptance/gpu/ly_lyc_write-GS.gb
![REGISTERS
A: 07 F: 00
B: 00 C: 01
D: 01 E: 00
H: C2 L: C2
ASSERTIONS
A: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly_lyc_write-GS.png)
👍
dmgCacceptance/gpu/ly_new_frame-GS.gb
![REGISTERS
A: 98 F: 10
B: 99 C: 81
D: 00 E: 81
H: 00 L: 81
ASSERTIONS
A: OK F: OK
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_ly_new_frame-GS.png)
👍
dmgCacceptance/gpu/stat_write_if-GS.gb
![TEST OK](img/dmgC_stat_write_if-GS.png)
👍
dmgCacceptance/gpu/vblank_if_timing.gb
![REGISTERS
A: FF F: 00
B: E0 C: E1
D: E1 E: 90
H: 91 L: FF
ASSERTIONS
B: OK C: OK
D: OK E: OK
H: OK](img/dmgC_vblank_if_timing.png)
👍
dmgCacceptance/timer/timer_if.gb
![REGISTERS
A: FF F: 00
B: FE C: FF
D: E0 E: E4
H: FE L: FF
ASSERTIONS
B: OK C: OK
D: OK E: OK
H: OK L: OK](img/dmgC_timer_if.png)
👍
dmgCwx_enable_midline.gb
👍
dmgCwy_enable_midline.gb
👍
dmgCapu/channel_3/channel_3_wave_ram_locked_write.gb
![#](img/dmgC_channel_3_wave_ram_locked_write.png)
👍
dmgCppu/lyc-GScgb0BC.gb
![! ! ! 0 ! ! ! !
! ! ! 0 ! ! ! !
! ! ! 0 ! ! ! !
! ! ! 0 ! ! ! !
) ) ) 0 * * * *
* * * 0 * * * *
* * * 0 ! 0 ! !
! ! ! ! ! ! ! !
! ! ! 0 ! ! ! !](img/dmgC_lyc-GScgb0BC.png)
👍
dmgCppu/stat_bug_GS.gb
![/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /](img/dmgC_stat_bug_GS.png)
👍
dmgCppu/stat_bug_with_lines_GS.gb
![/ / / / / / / /
/ / / / / / / /
/ / / / ! ! ! !](img/dmgC_stat_bug_with_lines_GS.png)
👍
dmgCppu/stat_write_conflict_GS.gb
![/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /](img/dmgC_stat_write_conflict_GS.png)
👍
cgb0apu/channel_1/channel_1_extra_length_clocking-cgb0B.gb
![0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgb0_channel_1_extra_length_clocking-cgb0B.png)
👍
cgb0apu/channel_2/channel_2_extra_length_clocking-cgb0B.gb
![0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgb0_channel_2_extra_length_clocking-cgb0B.png)
👍
cgb0apu/channel_3/channel_3_extra_length_clocking-cgb0.gb
![0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgb0_channel_3_extra_length_clocking-cgb0.png)
👍
cgb0apu/channel_4/channel_4_extra_length_clocking-cgb0B.gb
![0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgb0_channel_4_extra_length_clocking-cgb0B.png)
👍
cgbBapu/channel_1/channel_1_extra_length_clocking-cgb0B.gb
![0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgbB_channel_1_extra_length_clocking-cgb0B.png)
👍
cgbBapu/channel_2/channel_2_extra_length_clocking-cgb0B.gb
![0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgbB_channel_2_extra_length_clocking-cgb0B.png)
👍
cgbBapu/channel_3/channel_3_extra_length_clocking-cgbB.gb
![0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgbB_channel_3_extra_length_clocking-cgbB.png)
👍
cgbBapu/channel_4/channel_4_extra_length_clocking-cgb0B.gb
![0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgbB_channel_4_extra_length_clocking-cgb0B.png)
👍
cgbCppu/lyc-GScgb0BC.gb
![! ! ! 0 ! ! ! !
! ! ! 0 ! ! ! !
! ! ! 0 ! ! ! !
! ! ! 0 ! ! ! !
) ) ) 0 * * * *
* * * 0 * * * *
* * * 0 ! 0 ! !
! ! ! ! ! ! ! !
! ! ! 0 ! ! ! !](img/cgbC_lyc-GScgb0BC.png)
👍
cgbCppu/stat_write_conflict-cgb0BC.gb
![/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /](img/cgbC_stat_write_conflict-cgb0BC.png)
👍
cgbDppu/lyc_cgbDE.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
) ) ) ) * * * *
* * * * * * * *
* * * * ! * ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbD_lyc_cgbDE.png)
👍
cgbDppu/stat_write_conflict-cgbD.gb
![/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /](img/cgbD_stat_write_conflict-cgbD.png)
👍
cgbEapu/channel_1/channel_1_align.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_align.png)
👍
cgbEapu/channel_1/channel_1_align_cpu.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_align_cpu.png)
👍
cgbEapu/channel_1/channel_1_delay.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_delay.png)
👍
cgbEapu/channel_1/channel_1_duty.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_duty.png)
👍
cgbEapu/channel_1/channel_1_duty_delay.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_duty_delay.png)
👍
cgbEapu/channel_1/channel_1_freq_change.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_freq_change.png)
❌
cgbEapu/channel_1/channel_1_nrx2_glitch.gb
![! ! ! ! ! ! ! !
! ! ! ! ! RAR?RA](img/cgbE_channel_1_nrx2_glitch.png)
❌
cgbEapu/channel_1/channel_1_nrx2_speed_change.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! R3R3R3R3R3R3R3
! R3R3R3R3R3R3R3
! R3R3R3R3R3R3R3
! ! R3R3R3R3R3R3
R3R3R3R3R3R3R3R3
! R3R3R3R3R3R3R3
R3R3R3R3R3R3R3R3](img/cgbE_channel_1_nrx2_speed_change.png)
👍
cgbEapu/channel_1/channel_1_restart.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_restart.png)
👍
cgbEapu/channel_1/channel_1_restart_nrx2_glitch.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_restart_nrx2_glitch.png)
👍
cgbEapu/channel_1/channel_1_stop_div.gb
![](img/cgbE_channel_1_stop_div.png)
👍
cgbEapu/channel_1/channel_1_stop_restart.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_stop_restart.png)
❌
cgbEapu/channel_1/channel_1_sweep.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
R2R2R2R2R2R2R2R2
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_sweep.png)
❌
cgbEapu/channel_1/channel_1_sweep_restart.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! R2R2R2!
! ! ! ! ! ! ! !
R2R2R2R2R2R2R2R2
R2R2! ! ! ! R2R2
R2R2R2R2R2! ! !
! ! ! ! ! ! ! !
R2R2R2R2R2! ! !
! ! ! ! ! ! ! !
a2a2a2a2a2a2a20
0 0 0 0 0 0 0 0
a2a2a2a2a2a2a2a2
a2a2a2a2a2a2a2a2
a2a2a2a2a20 0 0
0 0 0 0 0 0 0 0
a2a2a2a2a20 0 0
0 0 0 0 0 0 0 0](img/cgbE_channel_1_sweep_restart.png)
❌
cgbEapu/channel_1/channel_1_sweep_restart_2.gb
![0 a20 0 0 0 0 0
0 0 0 0 0 0 0 0
a2a2a2a2a2a2a2a2
a2a2a2a2a2a2a2a2
a2a2a2a2a2a2a2a2
a2a2a2a2a2a2a2a2
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgbE_channel_1_sweep_restart_2.png)
👍
cgbEapu/channel_1/channel_1_volume.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_1_volume.png)
👍
cgbEapu/channel_1/channel_1_volume_div.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
0 0 ! ! ! ! ! !
0 0 ! ! ! ! ! !
0 0 ! ! ! ! ! !
0 0 ! ! ! ! ! !](img/cgbE_channel_1_volume_div.png)
👍
cgbEapu/channel_2/channel_2_align.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ) ) )
! ! ! ! ! ! ! !
! ! ! ! ) ) ) )
! ! ! ! ! ! ! !
! ! ! ! ) ) ) )](img/cgbE_channel_2_align.png)
👍
cgbEapu/channel_2/channel_2_align_cpu.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ) ) )
! ! ! ! ! ! ! !
! ! ! ! ! ) ) )
! ! ! ! ! ! ! !
! ! ! ! ! ) ) )](img/cgbE_channel_2_align_cpu.png)
👍
cgbEapu/channel_2/channel_2_delay.gb
![! ) ) ) ) ) ) !
! ) ) ) ) ) ) !
! ! ) ) ) ) ) )
) ) ) ) ) ) ! !](img/cgbE_channel_2_delay.png)
👍
cgbEapu/channel_2/channel_2_duty.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
) ) ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
) ) ) ) ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ) ) ) )
) ) ) ) ! ! ! !
! ! ! ! ) ) ) )
! ! ! ! ) ) ) )
) ) ) ) ) ) ) )
! ! ! ! ) ) ) )
) ) ) ) ) ) ) )](img/cgbE_channel_2_duty.png)
👍
cgbEapu/channel_2/channel_2_duty_delay.gb
![! ! ! ! ! ! ) )
) ) ) ) ) ) ) )
) ) ) ) ) ) ) )
) ) ) ) ) ) ) )
) ) ) ) ) ) ) )
) ) ) ) ) ) ) )
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) ) ) ) ) ) ! !
) ) ) ) ) ) ! !
) ) ) ) ) ) ! !
) ) ) ) ) ) ) )
! ! ! ! ! ! ! !](img/cgbE_channel_2_duty_delay.png)
👍
cgbEapu/channel_2/channel_2_freq_change.gb
![! ! ! ! ! ! ! !
! ! ) ) ) ) ) )
! ! ! ! ! ! ! !
! ) ) ) ) ) ) )
! ! ! ! ! ! ! !
) ) ) ) ) ) ) )
! ! ! ! ! ! ! )
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! ! ! ) ) ) ) !
! ! ! ) ) ) ) !](img/cgbE_channel_2_freq_change.png)
❌
cgbEapu/channel_2/channel_2_nrx2_glitch.gb
![#](img/cgbE_channel_2_nrx2_glitch.png)
❌
cgbEapu/channel_2/channel_2_nrx2_speed_change.gb
![!](img/cgbE_channel_2_nrx2_speed_change.png)
👍
cgbEapu/channel_2/channel_2_restart.gb
![! ! ! ! ! ! ! !
! ! ! ) ) ) ) )
! ! ! ! ! ! ! !
! ! ! ) ) ) ) )
! ! ! ! ! ! ! )
) ) ) ) ) ) ) )
! ! ! ! ! ! ! )
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! ! ! ) ) ) ) )
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) ) ) ) ) ) ) )
) ) ) ) ) ) ) !
) ) ) ) ) ) ) )
) ) ) ) ) ) ) !
) ) ) ) ) ) ) )
) ) ) ! ! ! ! !](img/cgbE_channel_2_restart.png)
👍
cgbEapu/channel_2/channel_2_restart_nrx2_glitch.gb
![# # # # # # # #
# # # # # # # !](img/cgbE_channel_2_restart_nrx2_glitch.png)
👍
cgbEapu/channel_2/channel_2_stop_div.gb
![](img/cgbE_channel_2_stop_div.png)
👍
cgbEapu/channel_2/channel_2_stop_restart.gb
![! ! ! ! ! ! ! !
! ! ! ! ) ) ) )
! ! ! ! ! ! ! !
! ! ! ! ) ) ) )
! ! ! ! ! ! ! !
) ) ) ) ) ) ) )
! ! ! ! ! ! ! !
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! ! ! ! ) ) ) )
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! ! ! ! ) ) ) )
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) ) ) ) ) ) ) )
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) ) ) ) ) ) ) )
) ) ) ) ) ) ) )
) ) ) ) ) ) ) )
) ) ) ) ! ! ! !](img/cgbE_channel_2_stop_restart.png)
👍
cgbEapu/channel_2/channel_2_volume.gb
![) ) ! ! ) ) ) )](img/cgbE_channel_2_volume.png)
👍
cgbEapu/channel_2/channel_2_volume_div.gb
![) ) ( ( ( ! ! !
) ) ( ( ( ! ! !
0 0 ! ! ! ! ! !
0 0 ! ! ! ! ! !](img/cgbE_channel_2_volume_div.png)
👍
cgbEapu/channel_3/channel_3_and_glitch.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_3_and_glitch.png)
👍
cgbEapu/channel_3/channel_3_delay.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_3_delay.png)
👍
cgbEapu/channel_3/channel_3_first_sample.gb
![! ! ! ! ! ! ! !](img/cgbE_channel_3_first_sample.png)
👍
cgbEapu/channel_3/channel_3_freq_change_delay.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_3_freq_change_delay.png)
👍
cgbEapu/channel_3/channel_3_restart_delay.gb
![! ! ! ! ! ! ! !](img/cgbE_channel_3_restart_delay.png)
👍
cgbEapu/channel_3/channel_3_restart_during_delay.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_channel_3_restart_during_delay.png)
👍
cgbEapu/channel_3/channel_3_restart_stop_delay.gb
![! ! ! ! ! ! ! !](img/cgbE_channel_3_restart_stop_delay.png)
👍
cgbEapu/channel_3/channel_3_shift_delay.gb
![! ! ! ! ! ! ! !](img/cgbE_channel_3_shift_delay.png)
👍
cgbEapu/channel_3/channel_3_shift_skip_delay.gb
![! ! ! ! ! ! ! !](img/cgbE_channel_3_shift_skip_delay.png)
👍
cgbEapu/channel_3/channel_3_stop_delay.gb
![! ! ! ! ! ! ! !](img/cgbE_channel_3_stop_delay.png)
👍
cgbEapu/channel_3/channel_3_stop_div.gb
![$ $ % % , , - -
, , - - ( ( ) )
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgbE_channel_3_stop_div.png)
👍
cgbEapu/channel_3/channel_3_wave_ram_locked_write.gb
![#](img/cgbE_channel_3_wave_ram_locked_write.png)
👍
cgbEapu/channel_3/channel_3_wave_ram_sync.gb
![! ! ! ! ! ! ! !](img/cgbE_channel_3_wave_ram_sync.png)
👍
cgbEapu/channel_4/channel_4_align.gb
![! ! ! ! ! ! ! !
! ! ! ! 0 0 0 0
! ! ! ! ! ! ! !
! ! ! ! ! 0 0 0
! ! ! ! ! ! ! !
! ! ! ! 0 0 0 0
! ! ! ! ! ! ! !
! ! ! ! ! 0 0 0](img/cgbE_channel_4_align.png)
❌
cgbEapu/channel_4/channel_4_delay.gb
![! ! ! ! ! 0 0 0
! ! ! ! ! 0 0 0
! ! R20 0 0 0 0
! ! ! ! R2R2R20](img/cgbE_channel_4_delay.png)
❌
cgbEapu/channel_4/channel_4_equivalent_frequencies.gb
![0 0 0 0 0 0 0 a2
a2a2a2a2a2a2a2!
! ! ! ! ! ! ! R2
R2R2R2R2R2R2R20
0 0 0 0 0 0 0 a2
a2a2a2a2a2a2a2!
! ! ! ! ! ! ! R2
R2R2R2R2R2R2R20
0 0 0 0 0 0 0 0
0 a2a2a2a2a2a2!
! ! ! ! ! ! ! !
! R2R2R2R2R2R20
0 0 0 0 0 0 0 0
a2a2a2a2a2a2a2!
! ! ! ! ! ! ! !
R2R2R2R2R2R2R20](img/cgbE_channel_4_equivalent_frequencies.png)
❌
cgbEapu/channel_4/channel_4_freq_change.gb
![0 0 a2a2a2a2a2a2
0 0 0 0 0 a2a2a2
0 a2a2a2a2a2a2a2
0 0 0 0 0 0 a2a2
0 a2! ! ! ! ! !
0 a2a2a2a2a2a2a2
0 a2! ! ! ! ! !
0 0 0 a2a2a2a2a2](img/cgbE_channel_4_freq_change.png)
❌
cgbEapu/channel_4/channel_4_frequency_alignment.gb
![! ! ! 0 0 0 0 0
! ! R20 0 0 0 0
! ! ! R2R2R2R20
! ! ! ! R2R2R20
! ! ! ! ! R2R2R2
! ! ! R2R2R2R2R2
! ! ! R2R2R2R2R2
! ! ! ! ! R2R2R2
! ! ! ! R2R2R2R2
! ! R20 0 0 0 0
! ! R20 0 0 0 0
! ! ! ! R2R2R20
! ! ! ! R2R2R20
! ! ! ! ! ! R2R2
! ! ! ! R2R2R2R2
! ! ! ! R2R2R2R2
! ! ! ! R2R2R2R2
! ! ! ! R2R2R2R2](img/cgbE_channel_4_frequency_alignment.png)
👍
cgbEapu/channel_4/channel_4_lfsr.gb
![( $ & ' ( ( ( $](img/cgbE_channel_4_lfsr.png)
👍
cgbEapu/channel_4/channel_4_lfsr15.gb
![! ! ! ) - / 0 0
0 0 0 0 0 0 0 0
0 ( , . / 0 0 0
0 0 0 0 0 0 0 (
$ * - / 0 0 0 0
0 0 0 0 0 ( , &
+ . / 0 0 0 0 0
0 0 0 ( $](img/cgbE_channel_4_lfsr15.png)
👍
cgbEapu/channel_4/channel_4_lfsr_15_7.gb
![0 0 0 0 ! ! 0 0
0 0 ! 0 ! 0 0 0
! ! ! ! 0 0 ! 0
0 0 ! 0 ! ! 0 0
0 0 ! 0 ! ! 0 0
! ! ! 0 ! 0 ! 0
0 ! ! ! ! ! 0 !
0 0 0 0 ! ! ! 0
0 0 ! 0 0 ! 0 0
! ! 0 ! ! 0 ! 0
! ! 0 ! ! ! ! 0
! ! 0 0 0 ! ! 0
! 0 0 ! 0 ! ! !
0 ! ! ! 0 0 ! !
0 0 ! 0 ! 0 ! 0
! ! ! ! ! ! ! 0](img/cgbE_channel_4_lfsr_15_7.png)
👍
cgbEapu/channel_4/channel_4_lfsr_7_15.gb
![0 ! ! ! 0 0 0 0
0 ! ! ! 0 0 0 !
0 0 ! 0 0 0 0 !
0 0 ! 0 0 ! ! 0
0 0 ! 0 0 ! ! 0
! ! 0 0 0 ! ! 0
! ! 0 ! 0 ! ! 0
! 0 0 ! 0 ! ! 0
! ! ! ! 0 ! ! !
0 ! ! ! 0 ! ! 0
0 0 ! ! 0 0 ! !
0 0 ! ! 0 ! 0 0
! 0 ! 0 ! 0 ! 0
! 0 ! ! ! 0 ! !
! ! ! ! ! ! ! !
! 0 0 ! ! 0 0 0](img/cgbE_channel_4_lfsr_7_15.png)
👍
cgbEapu/channel_4/channel_4_lfsr_restart.gb
![( ( $ & ' ( ( (
$](img/cgbE_channel_4_lfsr_restart.png)
👍
cgbEapu/channel_4/channel_4_lfsr_restart_fast.gb
![( ( $ & ' ( ( (
$](img/cgbE_channel_4_lfsr_restart_fast.png)
👍
cgbEapu/channel_4/channel_4_volume_div.gb
![) ) ( ( ( ( ( (
) ) ( ( ( ( ( (
( ( ( ( ( ( ( (
( ( ( ( ( ( ( (
0 0 ! ! ! ! ! !
0 0 ! ! ! ! ! !
0 0 ! ! ! ! ! !
0 0 ! ! ! ! ! !](img/cgbE_channel_4_volume_div.png)
👍
cgbEapu/div_trigger_volume_10.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_div_trigger_volume_10.png)
👍
cgbEapu/div_write_trigger.gb
![0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0](img/cgbE_div_write_trigger.png)
❌
cgbEapu/div_write_trigger_10.gb
![0 0 a2a2a2a2a2a2
a2a2a2a2a2a2a2a2
0 0 a3a30 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 a3a30 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 a3a3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
a3a30 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 a3a30 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 a3a30 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 a3a3](img/cgbE_div_write_trigger_10.png)
👍
cgbEapu/div_write_trigger_volume.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_div_write_trigger_volume.png)
👍
cgbEapu/div_write_trigger_volume_10.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_div_write_trigger_volume_10.png)
👍
cgbEdma/gbc_dma_cont.gb
![! - ! - ! - ! -
! - ! - ! - ! -](img/cgbE_gbc_dma_cont.png)
👍
cgbEdma/gdma_addr_mask.gb
![! - ! - ! - ! -
! - ! - ! - ! -
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_gdma_addr_mask.png)
👍
cgbEdma/hdma_lcd_off.gb
![! - ! - ! - ! -
! - ! - ! - ! -
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ) ! ! ! ! ! !](img/cgbE_hdma_lcd_off.png)
👍
cgbEdma/hdma_mode0.gb
![! - ! - ! - ! -
! - ! - ! - ! -
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ) ! ! ! ! ! !](img/cgbE_hdma_mode0.png)
👍
cgbEppu/blocking_bgpi_increase.gb
![- - - - - - - -](img/cgbE_blocking_bgpi_increase.png)
👍
cgbEppu/lyc_cgbDE.gb
![! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !
) ) ) ) * * * *
* * * * * * * *
* * * * ! * ! !
! ! ! ! ! ! ! !
! ! ! ! ! ! ! !](img/cgbE_lyc_cgbDE.png)
👍
cgbEppu/stat_write_conflict-cgbE.gb
![/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /
/ / / / / / / /](img/cgbE_stat_write_conflict-cgbE.png)
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